Author of the publication

High level synthesis through folding of data flow graphs: Optimal intra-node scheduling.

, , and . Microprocess. Microprogramming, 39 (2-5): 89-92 (1993)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Mapping neural nets onto a massively parallel architecture: a defect-tolerance solution., , , and . Proc. IEEE, 79 (4): 444-460 (1991)DFG: a graph based approach for algorithmic flow driven architecture synthesis., and . Microprocessing and Microprogramming, 32 (1-5): 683-690 (1991)A behavioral level tool for design and verification of parallel architectures: PADS., and . Microprocess. Microprogramming, 38 (1-5): 723-730 (1993)Array partitioning to achieve defect tolerance., , and . EUROMICRO, page 487-491. IEEE Computer Society, (1997)A Channel-Constrained Reconfiguration Approach for Processing Arrays., , and . DFT, page 99-107. IEEE Computer Society, (1995)High level synthesis through folding of data flow graphs: Optimal intra-node scheduling., , and . Microprocess. Microprogramming, 39 (2-5): 89-92 (1993)APES: an integrated system for behavioral design, simulation and evaluation of array processors., and . ICCD, page 568-572. IEEE, (1988)Behavioral Simulation of Array Processors in the APES Environment., and . Simulation, 59 (4): 264-269 (1992)High level architectural synthesis: Precedence analysis and automatic cycle detection in data flow graphs., , and . Microprocess. Microprogramming, 40 (10-12): 693-696 (1994)Distributed Architecture Design to Match Optimum Process Allocation: A Simulated Annealing Based Approach., and . RTSS, page 114-123. IEEE Computer Society, (1987)