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Positivity, posynomials and tile size selection., and . SC, page 55. IEEE/ACM, (2008)A domain specific interconnect for reconfigurable computing., , and . LCTES, page 79-88. ACM, (2008)A model for fusion and code motion in an automatic parallelizing compiler., , , and . PACT, page 343-352. ACM, (2010)A Model for Fusion and Code Motion in an Automatic Parallelizing Compiler, , , and . Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques, page 343--352. New York, NY, USA, ACM, (2010)DMATiler: revisiting loop tiling for direct memory access., , , , , , and . PACT, page 559-560. ACM, (2010)Automatic creation of tile size selection models., , , , , and . CGO, page 190-199. ACM, (2010)A Geometric Programming Framework for Optimal Multi-Level Tiling., and . SC, page 18. IEEE Computer Society, (2004)Compact multi-dimensional kernel extraction for register tiling., , , , and . SC, ACM, (2009)Multi-level tiling: M for the price of one., , , , and . SC, page 51. ACM Press, (2007)Parameterized tiled loops for free., , , and . PLDI, page 405-414. ACM, (2007)