Author of the publication

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

3D V-Cache: the Implementation of a Hybrid-Bonded 64MB Stacked Cache for a 7nm x86-64 CPU.

J. Wuu, R. Agarwal, M. Ciraula, C. Dietz, B. Johnson, D. Johnson, R. Schreiber, R. Swaminathan, W. Walker, and S. Naffziger. ISSCC, page 428-429. IEEE, (2022)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Colin Davenport

Genomic and metagenomic application of microbial genome signaturesC. Davenport. MedH Hannover, (2009)

Anand Dave

Dave Toney

Dave Berry

Dave Davis

Other publications of authors with the same name

De-layering the Data Network.D. Johnson, and N. Hayman. DRCN, page 317-322. IEEE, (2001)4.8 A 28nm x86 APU optimized for power and area efficiency.K. Wilcox, D. Akeson, H. III, J. Farrell, D. Johnson, G. Krishnan, H. McIntyre, E. McLellan, S. Naffziger, R. Schreiber and 2 other author(s). ISSCC, page 1-3. IEEE, (2015)"Zen 4": The AMD 5nm 5.7GHz x86-64 Microprocessor Core.B. Munger, K. Wilcox, J. Sniderman, C. Tung, B. Johnson, R. Schreiber, C. Henrion, K. Gillespie, T. Burd, H. III and 10 other author(s). ISSCC, page 38-39. IEEE, (2023)Micropipelined asynchronous discrete cosine transform (DCT/IDCT) processor.D. Johnson, V. Akella, and B. Stott. IEEE Trans. Very Large Scale Integr. Syst., 6 (4): 731-740 (1998)Intel iAPX 432: VLSI building blocks for a fault-tolerant computer.D. Johnson, D. Budde, D. Carson, and C. Peterson. AFIPS National Computer Conference, page 531-537. AFIPS Press, (1983)Design solutions for the Bulldozer 32nm SOI 2-core processor module in an 8-core CPU.T. Fischer, S. Arekapudi, E. Busta, C. Dietz, M. Golden, S. Hilker, A. Horiuchi, K. Hurd, D. Johnson, H. McIntyre and 4 other author(s). ISSCC, page 78-80. IEEE, (2011)A VLSI-intensive fault-tolerant computer architecture.F. Pollack, D. Johnson, D. Carson, R. Ebersole, V. Kini, K. Lai, B. Silvernail, and S. Stacey. Compcon, page 134-142. IEEE Computer Society, (1990)Asynchronous 2-D discrete cosine transform core processor.B. Stott, D. Johnson, and V. Akella. ICCD, page 380-385. IEEE Computer Society, (1995)Radiometric Noise Assessment of the Cross-Track Infrared Sounder on the NOAA-20 Satellite.D. Tremblay, F. Iturbide-Sanchez, Y. Chen, L. Borg, J. Predina, X. Jin, D. Tobin, L. Strow, D. Mooney, D. Johnson and 2 other author(s). IEEE Trans. Geosci. Remote. Sens., (2022)The evolution of a reliable transport network.D. Johnson, N. Hayman, and P. Veitch. IEEE Commun. Mag., 37 (8): 52-57 (1999)

BibSonomy

Disambiguation of "Johnson, Dave"

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

3D V-Cache: the Implementation of a Hybrid-Bonded 64MB Stacked Cache for a 7nm x86-64 CPU.

Please choose a person to relate this publication to

Colin Davenport

Anand Dave

Dave Toney

Dave Berry

Dave Davis

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Johnson, Dave"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML 3D V-Cache: the Implementation of a Hybrid-Bonded 64MB Stacked Cache for a 7nm x86-64 CPU.

Please choose a person to relate this publication to

Colin Davenport

Anand Dave

Dave Toney

Dave Berry

Dave Davis

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

3D V-Cache: the Implementation of a Hybrid-Bonded 64MB Stacked Cache for a 7nm x86-64 CPU.