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An fpga based architecture for native protocol testing of multi-gbps source-synchronous devices.

. Georgia Institute of Technology, Atlanta, GA, USA, (2012)base-search.net (ftgeorgiatech:oai:smartech.gatech.edu:1853/44858).

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An fpga based architecture for native protocol testing of multi-gbps source-synchronous devices.. Georgia Institute of Technology, Atlanta, GA, USA, (2012)base-search.net (ftgeorgiatech:oai:smartech.gatech.edu:1853/44858).Practical methods for extending ATE to 40 and 50Gbps., , , and . ITC, page 1-10. IEEE Computer Society, (2013)Multi-gigahertz arbitrary timing generator and data pattern serializer/formatter., , , , , , and . ITC, page 1-11. IEEE Computer Society, (2012)Two methods for 24 Gbps test signal synthesis., and . DATE, page 579-582. IEEE, (2011)Extending a DWDM Optical Network Test System to 12 Gbps x4 Channels., and . J. Electron. Test., 27 (3): 351-361 (2011)