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A High IIP2 SAW-Less Superheterodyne Receiver With Multistage Harmonic Rejection.

, , , , and . IEEE J. Solid State Circuits, 51 (2): 332-347 (2016)

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A 1-V 84-dB DR 1-MHz bandwidth cascade 3-1 Delta-Sigma ADC in 65-nm CMOS., and . ESSCIRC, page 332-335. IEEE, (2009)A High IIP2 SAW-Less Superheterodyne Receiver With Multistage Harmonic Rejection., , , , and . IEEE J. Solid State Circuits, 51 (2): 332-347 (2016)A TDD/FDD SAW-less superheterodyne receiver with blocker-resilient band-pass filter and multi-stage HR in 28nm CMOS., , , , and . VLSIC, page 308-. IEEE, (2015)13.4 All-digital RF transmitter in 28nm CMOS with programmable RX-band noise shaping., , , , , , , , , and . ISSCC, page 222-223. IEEE, (2017)Design Considerations for Cascade Delta Sigma ADC's., and . IEEE Trans. Circuits Syst. II Express Briefs, 55-II (5): 389-393 (2008)A Novel Bootstrapped Switch Design, Applied in a 400 MHz Clocked ΔΣ ADC., and . ICECS, page 1156-1159. IEEE, (2006)All-Digital LTE SAW-Less Transmitter With DSP-Based Programming of RX-Band Noise., , , , , , , , , and . IEEE J. Solid State Circuits, 52 (12): 3434-3445 (2017)A fully-integrated 0.18µm CMOS DC-DC step-up converter, using a bondwire spiral inductor., , and . ESSCIRC, page 268-271. IEEE, (2007)A 0.18μm CMOS switched capacitor voltage modulator., , and . ESSCIRC, page 375-378. IEEE, (2005)Analysis and Performance Comparison of a Cascade 3-1 Delta-Sigma Topology., and . ICECS, page 222-225. IEEE, (2007)