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Disambiguation of "Bardon, Marie Garcia"

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Dimensioning for power and performance under 10nm: The limits of FinFETs scaling.

, , , , , , , and . ICICDT, page 1-4. IEEE, (2015)

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Andreas García Bardon

Andreas Garcia Bardon

Annie Bardon

Luisa García García

Sarahi Garcia Garcia

 

Other publications of authors with the same name

Dimensioning for power and performance under 10nm: The limits of FinFETs scaling., , , , , , , and . ICICDT, page 1-4. IEEE, (2015)Comparison of NBTI aging on adder architectures and ring oscillators in the downscaling technology nodes., , , , , , , , , and 5 other author(s). Microprocess. Microsystems, 39 (8): 1039-1051 (2015)STT-MRAM Stochastic and Defects-aware DTCO for Last Level Cache at Advanced Process Nodes., , , , , , , , and . ESSDERC, page 97-100. IEEE, (2023)STI and eSiGe source/drain epitaxy induced stress modeling in 28 nm technology with replacement gate (RMG) process., , , , , , , , and . ESSDERC, page 159-162. IEEE, (2013)Lateral NWFET optimization for beyond 7nm nodes., , , , , , , , , and 3 other author(s). ICICDT, page 1-4. IEEE, (2015)5nm: Has the time for a device change come?, , , , , , , and . ISQED, page 275-277. IEEE, (2016)Design Technology co-optimization for N10., , , , , , , , , and 18 other author(s). CICC, page 1-8. IEEE, (2014)Circuit Design for Bias Compatibility in Novel FinFET-Based Floating-Body RAM., , , , , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 57-II (3): 183-187 (2010)Design exploration of IGZO diode based VCMA array design for Storage Class Memory Applications., , , , , , , and . ESSDERC, page 241-244. IEEE, (2022)PPA and Scaling Potential of Backside Power Options in N2 and A14 Nanosheet Technology., , , , , , , , , and . VLSI Technology and Circuits, page 1-2. IEEE, (2023)