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Migration of a Dual Granularity Globally Interconnected PLD Architecture to a 0.5 µm TLM Process.

, , , , , , , , and . FPL, volume 975 of Lecture Notes in Computer Science, page 15-20. Springer, (1995)

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A silicon efficient FLEX 6000 programmable logic architecture., , , , , , , , and . CICC, page 273-276. IEEE, (1998)The StratixTM routing and logic architecture., , , , , , , , , and 4 other author(s). FPGA, page 12-20. ACM, (2003)The Stratix II logic and routing architecture., , , , , , , , , and 13 other author(s). FPGA, page 14-20. ACM, (2005)A 100 MHz PLL Implemented on a 100K Gate Programmable Logic Device (Abstract)., , , , , , , , and . FPGA, page 256. ACM, (1998)Migration of a Dual Granularity Globally Interconnected PLD Architecture to a 0.5 µm TLM Process., , , , , , , , and . FPL, volume 975 of Lecture Notes in Computer Science, page 15-20. Springer, (1995)Receiver Offset Cancellation in 90-nm PLD Integrated SERDES., , , , , , and . CICC, page 265-267. IEEE, (2007)A next generation architecture optimized for high density system level integration., , , , , , , , , and 4 other author(s). CICC, page 175-178. IEEE, (1999)