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Disambiguation of "Bahn, Jun Ho"

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Design of a router for network-on-chip.

, , and . Int. J. High Perform. Syst. Archit., 1 (2): 98-105 (2007)

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Jun-Ho Won

Ute Bahn

Rudolf Bahn

Horst Bahn

Erika Bahn

 

Other publications of authors with the same name

A Generic Network Interface Architecture for a Networked Processor Array (NePA)., , , and . ARCS, volume 4934 of Lecture Notes in Computer Science, page 247-260. Springer, (2008)Parallel FFT Algorithms on Network-on-Chips., , , and . Journal of Circuits, Systems, and Computers, 18 (2): 255-269 (2009)Efficient Parallel Buffer Structure and Its Management Scheme for a Robust Network-on-Chip (NoC) Architecture., and . CSICC, volume 6 of Communications in Computer and Information Science, page 98-105. (2008)Design of a router for network-on-chip., , and . Int. J. High Perform. Syst. Archit., 1 (2): 98-105 (2007)Parallel processing for block ciphers on a fault tolerant networked processor array., , , , and . Int. J. High Perform. Syst. Archit., 2 (3/4): 156-167 (2010)Parallel LDPC Decoding on a Network-on-Chip Based Multiprocessor Platform., , and . SBAC-PAD, page 35-40. IEEE Computer Society, (2009)On Design and Analysis of a Feasible Network-on-Chip (NoC) Architecture., , and . ITNG, page 1033-1038. IEEE Computer Society, (2007)Parallel and Pipeline Processing for Block Cipher Algorithms on a Network-on-Chip., , , and . ITNG, page 849-854. IEEE Computer Society, (2009)Parallel FFT Algorithms on Network-on-Chips., , and . ITNG, page 1087-1093. IEEE Computer Society, (2008)On Design and Application Mapping of a Network-on-Chip(NoC) Architecture., , , , and . Parallel Process. Lett., 18 (2): 239-255 (2008)