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Disambiguation of "Zambreno, Joseph"

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Hardware Containers for Software Components: A Trusted Platform for COTS-Based Systems.

, , , , and . CSE (2), page 830-836. IEEE Computer Society, (2009)

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Julie Joseph

Joseph Landsberg

Joseph Kugbe

Joseph Dehler

Joseph Thomas

 

Other publications of authors with the same name

Improving System Predictability and Performance via Hardware Accelerated Data Structures., , , , , , and . ICCS, volume 9 of Procedia Computer Science, page 1197-1205. Elsevier, (2012)Design and Implementation of an FPGA Architecture for High-Speed Network Feature Extraction., , , , and . FPT, page 49-56. IEEE, (2007)A Reconfigurable Architecture for the Detection of Strongly Connected Components., , , and . ACM Trans. Reconfigurable Technol. Syst., 9 (2): 16:1-16:19 (2016)Exploring Area/Delay Tradeoffs in an AES FPGA Implementation., , and . FPL, volume 3203 of Lecture Notes in Computer Science, page 575-585. Springer, (2004)k-NN text classification using an FPGA-based sparse matrix vector multiplication accelerator., , , , , and . EIT, page 257-263. IEEE, (2015)An FPGA-based Hardware Accelerator for Iris Segmentation., , and . ReConFig, page 1-8. IEEE, (2018)Enhancing Compiler Techniques for Memory Energy Optimizations., , and . EMSOFT, volume 2491 of Lecture Notes in Computer Science, page 364-381. Springer, (2002)An I/O Bandwidth-Sensitive Sparse Matrix-Vector Multiplication Engine on FPGAs., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 59-I (1): 113-123 (2012)Scalable FastMDP for Pre-departure Airspace Reservation and Strategic De-conflict., , and . CoRR, (2020)RAMPS: A Reconfigurable Architecture for Minimal Perfect Sequencing., , , , and . IEEE Trans. Parallel Distributed Syst., 27 (10): 3029-3043 (2016)