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Resynthesis of Combinational Circuts for Path Count Reduction and for Path Delay Fault Testability.

, and . ED&TC, page 486-490. IEEE Computer Society, (1996)

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Testable Path Delay Fault Cover for Sequential Circuits., , and . J. Inf. Sci. Eng., 16 (5): 673-686 (2000)New Challenges in Delay Testing of Nanometer, Multigigahertz Designs., , , and . IEEE Des. Test Comput., 21 (3): 241-247 (2004)Estimation for maximum instantaneous current through supply lines for CMOS circuits., , and . IEEE Trans. Very Large Scale Integr. Syst., 8 (1): 61-73 (2000)Test program synthesis for path delay faults in microprocessor cores., , and . ITC, page 1080-1089. IEEE Computer Society, (2000)Diagnosis-Based Post-Silicon Timing Validation Using Statistical Tools and Methodologies., , , and . ITC, page 339-348. IEEE Computer Society, (2003)HyAC: A Hybrid Structural SAT Based ATPG for Crosstalk., , and . ITC, page 112-121. IEEE Computer Society, (2003)Testing High Speed VLSI Devices Using Slower Testers., , and . VTS, page 16-21. IEEE Computer Society, (1999)On Testing the Path Delay Faults of a Microprocessor Using its Instruction Set., , and . VTS, page 15-22. IEEE Computer Society, (2000)False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation., , , and . DAC, page 566-569. ACM, (2002)Embedded software-based self-testing for SoC design., , , , and . DAC, page 355-360. ACM, (2002)