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Disambiguation of "Tsui, Chi-Ying"

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A comprehensive and accurate latency model for Network-on-Chip performance analysis.

, , , , , and . ASP-DAC, page 323-328. IEEE, (2014)

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Ying Chi

Chi Lan Tsui

Matthew Tsui

Ying Ying

Tung Yu Tsui

 

Other publications of authors with the same name

Finite state machine partitioning for low power., and . ISCAS (1), page 306-309. IEEE, (1999)Design and implementation of high-speed arbiter for large scale VOQ crossbar switches., , and . ISCAS (2), page 308-311. IEEE, (2003)Low Complexity SST Viterbi Decoder., and . VTC Fall, page 1-2. IEEE, (2006)An Energy Efficient Layered Decoding Architecture for LDPC Decoder., and . IEEE Trans. Very Large Scale Integr. Syst., 18 (8): 1185-1195 (2010)The Design of a Micro Power Management System for Applications Using Photovoltaic Cells With the Maximum Output Power Control., , and . IEEE Trans. Very Large Scale Integr. Syst., 17 (8): 1138-1142 (2009)An efficient Network-on-Chip (NoC) based multicore platform for hierarchical parallel genetic algorithms., , , , , and . NOCS, page 17-24. IEEE, (2014)Low-latency approximate matrix inversion for high-throughput linear pre-coders in massive MIMO., and . VLSI-SoC, page 1-5. IEEE, (2016)A fault-tolerant network-on-chip design using dynamic reconfiguration of partial-faulty routing resources., , and . VLSI-SoC, page 192-195. IEEE, (2011)A thermal-aware application specific routing algorithm for Network-on-Chip design., and . ASP-DAC, page 449-454. IEEE, (2011)A Two-Staged Adaptive Successive Cancellation List Decoding for Polar Codes., , and . ISCAS, page 1-5. IEEE, (2019)