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Towards Efficient Deep Neural Network Training by FPGA-Based Batch-Level Parallelism., , , , , and . FCCM, page 45-52. IEEE, (2019)Optimizing CNN-based Segmentation with Deeply Customized Convolutional and Deconvolutional Architectures on FPGA., , , , , and . ACM Trans. Reconfigurable Technol. Syst., 11 (3): 19:1-19:22 (2018)Accelerating Bayesian Neural Networks via Algorithmic and Hardware Optimizations., , , , , and . IEEE Trans. Parallel Distributed Syst., 33 (12): 3387-3399 (2022)LL-GNN: Low Latency Graph Neural Networks on FPGAs for Particle Detectors., , , , , , and . CoRR, (2022)SAE: Single Architecture Ensemble Neural Networks., , and . CoRR, (2024)Enabling fast uncertainty estimation: accelerating bayesian transformers via algorithmic and hardware optimizations., , and . DAC, page 325-330. ACM, (2022)Optimizing quantum circuit placement via machine learning., , and . DAC, page 19-24. ACM, (2022)When Monte-Carlo Dropout Meets Multi-Exit: Optimizing Bayesian Neural Networks on FPGA., , , , , , and . DAC, page 1-6. IEEE, (2023)VINNAS: Variational Inference-based Neural Network Architecture Search., , and . CoRR, (2020)High-Performance FPGA-based Accelerator for Bayesian Recurrent Neural Networks., , , , and . CoRR, (2021)