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Transistor Level Synthesis Dedicated to Fast I.P. Prototyping.

, , , , , and . PATMOS, volume 2451 of Lecture Notes in Computer Science, page 156-166. Springer, (2002)

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Delay bound determination for timing closure satisfaction., , and . ISCAS (5), page 375-378. IEEE, (2001)Explicit evaluation of short circuit power dissipation for CMOS logic structures., , and . ISLPD, page 129-134. ACM, (1995)Temperature Dependence in Low Power CMOS UDSM Process., , , , and . PATMOS, volume 3254 of Lecture Notes in Computer Science, page 110-118. Springer, (2004)Post-layout timing simulation of CMOS circuits., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 12 (8): 1170-1177 (1993)Second Generation Delay Model for Submicron CMOS Process., , and . PATMOS, volume 1918 of Lecture Notes in Computer Science, page 159-167. Springer, (2000)Internal Power Dissipation Modeling and Minimization for Submicronic CMOS Design., , and . PATMOS, volume 1918 of Lecture Notes in Computer Science, page 129-138. Springer, (2000)P.SIZE: a sizing aid for optimized designs., , and . EURO-DAC, page 160-165. IEEE Computer Society Press, (1992)Delay bound based CMOS gate sizing technique., , , , and . ISCAS (5), page 189-192. IEEE, (2004)Delay modelling improvement for low voltage applications., , and . EURO-DAC, page 216-221. IEEE Computer Society, (1995)RF Interface Design Using Mixed-Mode Methodology., , , and . VLSI, volume 162 of IFIP Conference Proceedings, page 326-333. Kluwer, (1999)