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Disambiguation of "Busquets-Mataix, José V."

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Cache Contents Selection for Statically-Locked Instruction Caches: An Algorithm Comparison.

, , , and . ECRTS, page 49-56. IEEE Computer Society, (2005)

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Humberto Jorge José

Nadine José Gonzalez

José Navarrete

José Baena

José Teixeira

 

Other publications of authors with the same name

Using harmonic task-sets to increase the schedulable utilization of cache-based preemptive real-time systems., , , , and . RTCSA, page 195-202. IEEE Computer Society, (1996)Human-computer cooperation platform for developing real-time robotic applications., , , and . J. Supercomput., 75 (4): 1849-1868 (2019)Techniques to increase the schedulable utilization of cache-based preemptive real-time systems., , , and . J. Syst. Archit., 46 (4): 357-378 (2000)Architecture Extensions for Efficient Management of Scratch-Pad Memory., , and . PATMOS, volume 6951 of Lecture Notes in Computer Science, page 43-52. Springer, (2011)The impact of extrinsic cache performance on predictability of real-time systems., and . RTCSA, page 8-15. IEEE Computer Society, (1995)On Using Locking Caches in Embedded Real-Time Systems., , , , and . ICESS, volume 3820 of Lecture Notes in Computer Science, page 150-159. Springer, (2005)Adding Instruction Cache Effect to an Exact Schedulability Analysis of Preemptive Real-Time Systems., , , , and . RTS, page 271-276. IEEE Computer Society, (1996)Hybrid instruction cache partitioning for preemptive real-time systems., , and . RTS, page 56-63. IEEE Computer Society, (1997)Adding instruction cache effect to schedulability analysis of preemptive real-time systems., , , , and . IEEE Real Time Technology and Applications Symposium, page 204-212. IEEE Computer Society, (1996)Cache Contents Selection for Statically-Locked Instruction Caches: An Algorithm Comparison., , , and . ECRTS, page 49-56. IEEE Computer Society, (2005)