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A Case Study for Improving Performances of Deep-Learning Processor with MRAM., , , , , , , and . IPSJ Trans. Syst. LSI Des. Methodol., (2024)A super cut-off CMOS (SCCMOS) scheme for 0.5-V supply voltage with picoampere stand-by current., , and . IEEE J. Solid State Circuits, 35 (10): 1498-1501 (2000)Signal contributions to heavily diffusion-weighted functional magnetic resonance imaging investigated with multi-SE-EPI acquisitions., , , , , , , and . NeuroImage, (2014)A Wearable Healthcare System With a 13.7 µ A Noise Tolerant ECG Processor., , , , , , , , , and 1 other author(s). IEEE Trans. Biomed. Circuits Syst., 9 (5): 733-742 (2015)A 1.15-TOPS 6.57-TOPS/W Neural Network Processor for Multi-Scale Object Detection With Reduced Convolutional Operations., , , , , , , , , and . IEEE J. Sel. Top. Signal Process., 14 (4): 634-645 (2020)STT-MRAM Operating at 0.38V Using Negative-Resistance Sense Amplifier., , , , , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 97-A (12): 2411-2417 (2014)Multiple-Bit-Upset and Single-Bit-Upset Resilient 8T SRAM Bitcell Layout with Divided Wordline Structure., , , , and . IEICE Trans. Electron., 95-C (10): 1675-1681 (2012)A Low-Power Multi-Phase Oscillator with Transfer Gate Phase Coupler Enabling Even-Numbered Phase Output., , , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 94-A (12): 2701-2708 (2011)An Opampless Second-Order MASH ΔΣ ADC with Using Gated Ring Oscillator Time-to-Digital Converter., , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 96-A (2): 434-442 (2013)Area Optimization in 6T and 8T SRAM Cells Considering Vth Variation in Future Processes., , , , , , and . IEICE Trans. Electron., 90-C (10): 1949-1956 (2007)