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Multistandard FEC Decoders for Wireless Devices.

, , , and . IEEE Trans. Circuits Syst. II Express Briefs, 55-II (3): 284-288 (2008)

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Towards a guided design flow for heterogeneous reconfigurable architectures., and . FPL, page 1-2. IEEE, (2015)A Novel Routing Architecture for Field-Programmable Gate-Arrays., , and . ARCS, volume 4934 of Lecture Notes in Computer Science, page 144-158. Springer, (2008)Astra: An Advanced Space-Time Reconfigurable Architecture., , and . FPL, page 1-4. IEEE, (2006)A conceptual toolchain for an application domain specific reconfigurable logic architecture., and . ReConFig, page 1-4. IEEE, (2014)Improving FPGA placement with a self-organizing map., and . ReConFig, page 1-6. IEEE, (2013)Mapping A VLIWxSIMD Processor on an FPGA: Scalability and Performance., , and . FPL, page 521-524. IEEE, (2007)Reconfigurable cell architecture for multi-standard interleaving and deinterleaving in digital communication systems., , and . FPL, page 527-530. IEEE, (2008)A Novel Toolset for the Development of FPGA-like Reconfigurable Logic., , and . FPL, page 640-643. IEEE, (2005)Optimizing the Performance of the Simulated Annealing Based Placement Algorithms for Island-Style FPGAs., and . FPL, volume 3203 of Lecture Notes in Computer Science, page 852-856. Springer, (2004)Scalable reconfigurable channel decoder architecture for future wireless handsets., , and . DATE, page 1563-1568. EDA Consortium, San Jose, CA, USA, (2007)