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Disambiguation of "Hironaka, Tetsuo"

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Traf: A Graphical Proof Tree Viewer Cooperating with Coq Through Proof General.

, , , and . APLAS, volume 11275 of Lecture Notes in Computer Science, page 157-165. Springer, (2018)

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Tetsuo Morino

Tetsuo Kishimoto

 

Other publications of authors with the same name

Design of superscalar processor with multi-bank register file., , , , , , , and . ISCAS (4), page 3507-3510. IEEE, (2005)A novel hierarchical multi-port cache., , , , , and . ESSCIRC, page 405-408. IEEE, (2003)Compact 12-port multi-bank register file test-chip in 0.35µm CMOS for highly parallel processors., , , , , and . ASP-DAC, page 551-552. IEEE Computer Society, (2004)Unified Data/Instruction Cache with Hierarchical Multi-Port Architecture and Hidden Precharge Pipeline., , , , , and . APCCAS, page 1297-1300. IEEE, (2006)OSAIFU: A Source Code Factorizer on Android Studio., , , , and . ICSME, page 422-425. IEEE, (2019)Supporting Program Understanding by Automatic Indexing of Functionalities in Source Code., , , and . SERA, page 13-18. IEEE, (2019)A coarse-grained reconfigurable architecture with low cost configuration data compression mechanism., , and . FPT, page 311-314. IEEE, (2003)Traf: A Graphical Proof Tree Viewer Cooperating with Coq Through Proof General., , , and . APLAS, volume 11275 of Lecture Notes in Computer Science, page 157-165. Springer, (2018)EDA Environment for Evaluating a New Switch-Block-Free Reconfigurable Architecture., , , , , and . ReConFig, page 448-454. IEEE Computer Society, (2011)Extracting Inclusion Graphs of API Member Sets to Improve Searchability., , , , and . SERA, page 53-59. IEEE, (2019)