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Design and Implementation of a 4Kb STT-MRAM with Innovative 200nm Nano-ring Shaped MTJ.

, , , , , , , , , , , , and . ISLPED, page 4-9. ACM, (2016)

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Unleashing the potential of MLC STT-RAM caches., , , and . ICCAD, page 429-436. IEEE, (2013)Probabilistic design methodology to improve run-time stability and performance of STT-RAM caches., , , and . ICCAD, page 88-94. ACM, (2012)Design exploration of racetrack lower-level caches., , , and . ISLPED, page 263-266. ACM, (2014)Multi retention level STT-RAM cache designs with a dynamic refresh scheme., , , , , , and . MICRO, page 329-338. ACM, (2011)Array Organization and Data Management Exploration in Racetrack Memory., , , , and . IEEE Trans. Computers, 65 (4): 1041-1054 (2016)The evolutionary spintronic technologies and their usage in high performance computing., , and . SoCC, page 350-355. IEEE, (2015)Optimizing MLC-based STT-RAM caches by dynamic block size reconfiguration., , , , and . ICCD, page 133-138. IEEE Computer Society, (2014)STT-RAM designs supporting dual-port accesses., , and . DATE, page 853-858. EDA Consortium San Jose, CA, USA / ACM DL, (2013)An efficient STT-RAM-based register file in GPU architectures., , , , and . ASP-DAC, page 490-495. IEEE, (2015)Design and Implementation of a 4Kb STT-MRAM with Innovative 200nm Nano-ring Shaped MTJ., , , , , , , , , and 3 other author(s). ISLPED, page 4-9. ACM, (2016)