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Hardware acceleration in the IBM PowerEN processor: architecture and performance.

, , , , and . PACT, page 389-400. ACM, (2012)

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NetStorage: A synchronized trace-driven replayer for network-storage system evaluation., , , , , , and . Perform. Evaluation, (2019)Hardware acceleration in the IBM PowerEN processor: architecture and performance., , , , and . PACT, page 389-400. ACM, (2012)TraceRAR: An I/O Performance Evaluation Tool for Replaying, Analyzing, and Regenerating Traces., , , , and . NAS, page 1-10. IEEE Computer Society, (2017)Architecture and Performance of the Hardware Accelerators in IBM's PowerEN Processor., , , , and . ACM Trans. Parallel Comput., 1 (1): 5:1-5:26 (2014)A 440-ps 64-bit adder in 1.5-V/0.18-μm partially depleted SOI technology., , and . IEEE J. Solid State Circuits, 36 (10): 1546-1552 (2001)The Potential of Compile-Time Analysis to Adapt the Cache Coherence Enforcement Strategy to the Data Sharing Characteristics., and . IEEE Trans. Parallel Distributed Syst., 6 (5): 470-481 (1995)Write buffer design for cache-coherent shared-memory multiprocessors., and . ICCD, page 506-511. IEEE Computer Society, (1995)SOI Implementation of a 64-Bit Adder., , , and . ICCD, page 573-. IEEE Computer Society, (1999)A Compiler-Assisted Scheme for Adaptive Cache Coherence Enforcement., , , and . IFIP PACT, volume A-50 of IFIP Transactions, page 69-78. North-Holland, (1994)An evaluation of a compiler optimization for improving the performance of a coherence directory., , and . International Conference on Supercomputing, page 75-84. ACM, (1994)