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CHARSTAR: Clock Hierarchy Aware Resource Scaling in Tiled ARchitectures.

, and . ISCA, page 147-160. ACM, (2017)

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Constraint Graph Analysis of Multithreaded Programs., , and . J. Instruction-Level Parallelism, (2004)Energy-Efficient Bayesian Inference Using Bitstream Computing., , and . IEEE Comput. Archit. Lett., 22 (1): 37-40 (January 2023)SHASTA: Synergic HW-SW Architecture for Spatio-temporal Approximation., , and . ACM Trans. Archit. Code Optim., 17 (4): 25:1-25:26 (2020)Combating Aging with the Colt Duty Cycle Equalizer., , , and . MICRO, page 103-114. IEEE Computer Society, (2010)Correctly implementing value prediction in microprocessors that support multithreading or multiprocessing., , , , and . MICRO, page 328-337. ACM/IEEE Computer Society, (2001)On the value locality of store instructions., and . ISCA, page 182-191. IEEE Computer Society, (2000)Temporally silent stores., and . ASPLOS, page 30-41. ACM Press, (2002)TailWAG: Tail Latency Workload Analysis and Generation., and . BID@PPOPP, page 1:1-1:9. ACM, (2023)Recycling Data Slack in Out-of-Order Cores., and . HPCA, page 545-557. IEEE, (2019)Transparent mode flip-flops for collapsible pipelines., and . ICCD, page 553-560. IEEE, (2007)