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Fast Waveform Estimation (FWE) for Timing Analysis.

, and . IEEE Trans. Very Large Scale Integr. Syst., 19 (5): 846-856 (2011)

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Realizable reduction of interconnect circuits including self and mutual inductances., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 24 (2): 271-277 (2005)On-chip voltage regulator without physical inductor., , and . NEWCAS, page 105-108. IEEE, (2012)Partially Depleted Silicon-on-Ferroelectric Insulator Field Effect Transistor- Parametrization & Design Optimization for Minimum Subthreshold Swing., and . Microelectron. J., 46 (10): 981-987 (2015)Analysis of device capacitance and subthreshold behavior of Tri-gate SOI FinFET., and . Microelectron. J., (2017)Reliability and Energy Efficiency of the Tunneling Transistor-Based 6T SRAM Cell in Sub-10 nm Domain., and . IEEE Trans. Circuits Syst. II Express Briefs, 65-II (12): 1829-1833 (2018)Analysis of the current-voltage characteristics of Silicon on Ferroelectric Insulator Field Effect Transistor (SOF-FET)., and . SoCC, page 152-155. IEEE, (2014)A Low Leakage SRAM Bitcell Design Based on MOS-Type Graphene Nano-Ribbon FET., , , and . ISCAS, page 1-4. IEEE, (2019)An Asynchronous Reconfigurable Switched Capacitor Voltage Regulator., and . MWSCAS, page 1110-1113. IEEE, (2018)Impacts of signal slew and skew variations on delay uncertainty and crosstalk noise in coupled RLC global interconnects., , and . ICECS, page 1055-1058. IEEE, (2008)SecNVM: Power Side-Channel Elimination Using On-Chip Capacitors for Highly Secure Emerging NVM., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 29 (8): 1518-1528 (2021)