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A survey on decoding schedules of LDPC convolutional codes and associated hardware architectures.

, , , , and . ISCC, page 898-905. IEEE Computer Society, (2017)

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A Very High Throughput Deblocking Filter for H.264/AVC., , , and . J. Signal Process. Syst., 73 (2): 189-199 (2013)Fast Converging ADMM-Penalized Algorithm for LDPC Decoding., , , , and . IEEE Communications Letters, 20 (4): 648-651 (2016)High-Throughput Multi-Core LDPC Decoders Based on x86 Processor., and . IEEE Trans. Parallel Distributed Syst., 27 (5): 1373-1386 (2016)Model-based Design of Hardware SC Polar Decoders for FPGAs., , , and . ACM Trans. Reconfigurable Technol. Syst., 13 (2): 10:1-10:27 (2020)AFF3CT: A Fast Forward Error Correction Toolbox!, , , , , , , , , and 2 other author(s). SoftwareX, (2019)Bit-Width Optimizations for High-Level Synthesis of Digital Signal Processing Systems., , and . SiPS, page 280-285. IEEE, (2006)High-level synthesis for the design of FPGA-based signal processing systems., and . ICSAMOS, page 25-32. IEEE, (2009)Multicore implementation of LDPC decoders based on ADMM algorithm., , , , and . ICASSP, page 971-975. IEEE, (2016)High data rate and flexible hardware QC-LDPC decoder for satellite optical communications., , , and . ISTC, page 1-5. IEEE, (2018)Low-latency software LDPC decoders for x86 multi-core devices., and . SiPS, page 1-6. IEEE, (2017)