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Adding Temporal Redundancy to Delay Insensitive Codes to Mitigate Single Event Effects.

, , and . ASYNC, page 142-149. IEEE Computer Society, (2012)

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Evaluation of current QoS Mechanisms in Networks on Chip., , , and . SoC, page 1-4. IEEE, (2006)Evaluation on FPGA of triple rail logic robustness against DPA and DEMA., , , , , and . DATE, page 634-639. IEEE, (2009)NoC Power Estimation at the RTL Abstraction Level., , , , and . ISVLSI, page 475-478. IEEE Computer Society, (2008)Impact of C-elements in asynchronous circuits., , , and . ISQED, page 437-343. IEEE, (2012)Adding Temporal Redundancy to Delay Insensitive Codes to Mitigate Single Event Effects., , and . ASYNC, page 142-149. IEEE Computer Society, (2012)Evaluation of static and dynamic task mapping algorithms in NoC-based MPSoCs., , , and . SoC, page 87-90. IEEE, (2009)Lasio 3D NoC vertical links serialization: Evaluation of latency and buffer occupancy., , , , , and . SBCCI, page 1-6. IEEE, (2013)SPP-NIDS - A Sea of Processors Platform for Network Intrusion Detection Systems., , , , and . IEEE International Workshop on Rapid System Prototyping, page 27-33. IEEE Computer Society, (2007)PaDReH: a framework for the design and implementation of dynamically and partially reconfigurable systems., , , and . SBCCI, page 10-15. ACM, (2004)Triple Rail Logic Robustness against DPA., , , , , , and . ReConFig, page 415-420. IEEE Computer Society, (2008)