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Disambiguation of "Tudu, Jaynarayan T."

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On Securing Scan Design Through Test Vector Encryption.

, , , , and . ISCAS, page 1-5. IEEE, (2018)

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Ioana-Laura Tuduce

Oana Tudusciuc

T Peters

T Attin

T Neumann

 

Other publications of authors with the same name

ILP Based Approach for Input Vector Controlled (IVC) Toggle Maximization in Combinational Circuits., , and . VDAT, volume 7373 of Lecture Notes in Computer Science, page 172-179. Springer, (2012)A Cost Effective Technique for Diagnosis of Scan Chain Faults., , , and . VDAT, volume 711 of Communications in Computer and Information Science, page 191-204. Springer, (2017)Guided shifting of test pattern to minimize test time in serial scan., and . VDAT, page 1-6. IEEE, (2016)A high performance scan flip-flop design for serial and mixed mode scan test., , , and . IOLTS, page 233-238. IEEE, (2016)Securing Scan through Plain-text Restriction., , , , and . IOLTS, page 251-252. IEEE, (2019)JSCAN: A joint-scan DFT architecture to minimize test time, pattern volume, and power.. VDAT, page 1-6. IEEE, (2016)Graph theoretic approach for scan cell reordering to minimize peak shift power., , , and . ACM Great Lakes Symposium on VLSI, page 73-78. ACM, (2010)On Securing Scan Design Through Test Vector Encryption., , , , and . ISCAS, page 1-5. IEEE, (2018)Revisiting random access scan for effective enhancement of post-silicon observability., , , , and . IOLTS, page 132-137. IEEE, (2017)Scan cell reordering to minimize peak power during test cycle: A graph theoretic approach., , , and . European Test Symposium, page 259. IEEE Computer Society, (2010)