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A Distributed Control Path Architecture for VLIW Processors.

, , , and . IEEE PACT, page 197-206. IEEE Computer Society, (2005)

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Compilers for Instruction-Level Parallelism., , , , , and . Computer, 30 (12): 63-69 (1997)Profile-driven Instruction Level Parallel Scheduling with Application to Super Blocks., , , , , and . MICRO, page 58-67. ACM/IEEE Computer Society, (1996)Configurable optical interconnects for scalable datacenters., , , , and . OFC/NFOEC, page 1-3. IEEE, (2013)Parallelization of WHILE loops on pipelined architectures., , and . J. Supercomput., 5 (2-3): 119-136 (1991)Cydra 5.. Encyclopedia of Parallel Computing, Springer, (2011)Global Predicate Analysis and Its Application to Register Allocation., , , and . MICRO, page 114-125. ACM/IEEE Computer Society, (1996)Spill-free parallel scheduling of basic blocks., and . MICRO, page 119-124. ACM / IEEE Computer Society, (1995)Code generation schema for modulo scheduled loops., , and . MICRO, page 158-169. ACM / IEEE Computer Society, (1992)Embedded Computing: New Directions in Architecture and Automation., and . HiPC, volume 1970 of Lecture Notes in Computer Science, page 225-244. Springer, (2000)A microprogramming language for the B-1726., , and . MICRO, page 21-29. ACM, (1973)