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Global scheduling and register allocation based on predicated execution.

, and . ISCAS (3), page 232-235. IEEE, (2003)

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Chain-based pseudorandom tests for pre-silicon verification of CMP memory systems., , and . ICCD, page 552-559. IEEE Computer Society, (2016)A Constructive Method for Exploiting Code Motion., , , , and . ISSS, page 51-56. ACM / IEEE Computer Society, (1996)Mapping Data and Code into Scratchpads from Relocatable Binaries., , , and . ISVLSI, page 157-162. IEEE Computer Society, (2009)Global scheduling and register allocation based on predicated execution., and . ISCAS (3), page 232-235. IEEE, (2003)Exploiting Non-Critical Steiner Tree Branches for Post-Placement Timing Optimization., , , , and . ICCAD, page 528-535. IEEE, (2015)Timing-Driven Placement Based on Dynamic Net-Weighting for Efficient Slack Histogram Compression., , , , , and . ISPD, page 141-148. ACM, (2015)An Automatically-Retargetable Time-Constraint-Driven Instruction Scheduler for Post-compiling Optimization of Embedded Code., , and . SAMOS, volume 4599 of Lecture Notes in Computer Science, page 86-95. Springer, (2007)Pre-silicon verification of multiprocessor SoCs: The case for on-the-fly coherence/consistency checking., and . ICECS, page 843-846. IEEE, (2013)Spec&Check: An Approach to the Building of Shared-Memory Runtime Checkers for Multicore Chip Design Verification., , , and . ICCAD, page 1-7. ACM, (2019)Steep coverage-ascent directed test generation for shared-memory verification of multicore chips., , , and . ICCAD, page 29. ACM, (2018)