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A Volatile RRAM Synapse for Neuromorphic Computing.

E. Covi, D. Ielmini, Y. Lin, W. Wang, T. Stecconi, V. Milo, A. Bricalli, E. Ambrosi, G. Pedretti, and T. Tseng. ICECS, page 903-906. IEEE, (2019)

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Valerio Ketmaier

Milo Pejnovi

Peter Milo

Milo Brabínek

Milo Masalovi

Other publications of authors with the same name

Stochastic Learning in Neuromorphic Hardware via Spike Timing Dependent Plasticity With RRAM Synapses.G. Pedretti, V. Milo, S. Ambrogio, R. Carboni, S. Bianchi, A. Calderoni, N. Ramaswamy, A. Spinelli, and D. Ielmini. IEEE J. Emerg. Sel. Topics Circuits Syst., 8 (1): 77-85 (2018)End-to-end modeling of variability-aware neural networks based on resistive-switching memory arrays.A. Glukhov, N. Lepri, V. Milo, A. Baroni, C. Zambelli, P. Olivo, E. Pérez, C. Wenger, and D. Ielmini. VLSI-SoC, page 1-5. IEEE, (2022)Statistical model of program/verify algorithms in resistive-switching memories for in-memory neural network accelerators.A. Glukhov, V. Milo, A. Baroni, N. Lepri, C. Zambelli, P. Olivo, E. Pérez, C. Wenger, and D. Ielmini. IRPS, page 3. IEEE, (2022)A 4-Transistors/1-Resistor Hybrid Synapse Based on Resistive Switching Memory (RRAM) Capable of Spike-Rate-Dependent Plasticity (SRDP).V. Milo, G. Pedretti, R. Carboni, A. Calderoni, N. Ramaswamy, S. Ambrogio, and D. Ielmini. IEEE Trans. Very Large Scale Integr. Syst., 26 (12): 2806-2815 (2018)A Spiking Recurrent Neural Network with Phase Change Memory Synapses for Decision Making.G. Pedretti, V. Milo, S. Hashemkhani, P. Mannocci, O. Melnic, E. Chicca, and D. Ielmini. ISCAS, page 1-5. IEEE, (2020)Neuromorphic computing with hybrid memristive/CMOS synapses for real-time learning.D. Ielmini, S. Ambrogio, V. Milo, S. Balatti, and Z. Wang. ISCAS, page 1386-1389. IEEE, (2016)Brain-inspired recurrent neural network with plastic RRAM synapses.V. Milo, E. Chicca, and D. Ielmini. ISCAS, page 1-5. IEEE, (2018)Towards a Universal Model of Dielectric Breakdown.A. Padovani, P. Torraca, J. Strand, A. Shluger, V. Milo, and L. Larcher. IRPS, page 1-8. IEEE, (2023)Optimized programming algorithms for multilevel RRAM in hardware neural networks.V. Milo, F. Anzalone, C. Zambelli, E. Pérez, M. Mahadevaiah, O. Ossorio, P. Olivo, C. Wenger, and D. Ielmini. IRPS, page 1-6. IEEE, (2021)Low-energy inference machine with multilevel HfO2 RRAM arrays.V. Milo, C. Zambelli, P. Olivo, E. Pérez, O. Ossorio, C. Wenger, and D. Ielmini. ESSDERC, page 174-177. IEEE, (2019)

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Disambiguation of "Milo, Valerio"

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A Volatile RRAM Synapse for Neuromorphic Computing.

Please choose a person to relate this publication to

Valerio Ketmaier

Milo Pejnovi

Peter Milo

Milo Brabínek

Milo Masalovi

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Milo, Valerio"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A Volatile RRAM Synapse for Neuromorphic Computing.

Please choose a person to relate this publication to

Valerio Ketmaier

Milo Pejnovi

Peter Milo

Milo Brabínek

Milo Masalovi

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A Volatile RRAM Synapse for Neuromorphic Computing.