Author of the publication

An Architecture for Fault-Tolerant Computation with Stochastic Logic.

, , , , and . IEEE Trans. Computers, 60 (1): 93-105 (2011)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Hybrid binary-unary hardware accelerator., and . ASP-DAC, page 210-215. ACM, (2019)3D FPGAs: placement, routing, and architecture evaluation (abstract only)., , and . FPGA, page 263. ACM, (2005)Timing-driven partitioning-based placement for island style FPGAs., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 24 (3): 395-406 (2005)Parallel Unary Computing Based on Function Derivatives., , , and . ACM Trans. Reconfigurable Technol. Syst., 14 (1): 4:1-4:25 (2020)Placement and Routing in 3D Integrated Circuits., , , , , , and . IEEE Des. Test Comput., 22 (6): 520-531 (2005)Statistical Analysis and Design of HARP FPGAs., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (10): 2088-2102 (2006)Power and Area Efficient Sorting Networks Using Unary Processing., , , and . ICCD, page 125-128. IEEE Computer Society, (2017)Energy-Efficient Convolutional Neural Networks with Deterministic Bit-Stream Processing., , , , and . DATE, page 1757-1762. IEEE, (2019)Timing Minimization by Statistical Timing hMetis-based Partitioning., and . VLSI Design, page 58-63. IEEE Computer Society, (2003)Statistical Timing Driven Partitioning for VLSI Circuits., and . DATE, page 1109. IEEE Computer Society, (2002)