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Disambiguation of "Jung, Seong-Ook"

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A CNN-Based Super-Resolution Processor With Short-Term Caching for Real-Time UHD Upscaling.

, , and . IEEE Trans. Circuits Syst. I Regul. Pap., 71 (3): 1198-1207 (March 2024)

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Seong-Jung Kim

Ki-Chang Seong

Seunghyeon Seong

Nak-Hyon Seong

Hong-Jae Seong

 

Other publications of authors with the same name

STT-MRAM Sensing Circuit With Self-Body Biasing in Deep Submicron Technologies., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 22 (7): 1630-1634 (2014)Variation-Tolerant WL Driving Scheme for High-Capacity NAND Flash Memory., , , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 27 (8): 1828-1839 (2019)Noise constrained transistor sizing and power optimization for dual Vst domino logic., , and . IEEE Trans. Very Large Scale Integr. Syst., 10 (5): 532-541 (2002)Coupling delay optimization by temporal decorrelation using dual threshold voltage technique., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 11 (5): 879-887 (2003)Slope Interconnect Effort: Gate-Interconnect Interdependent Delay Modeling for Early CMOS Circuit Simulation., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 56-I (7): 1428-1441 (2009)Single Bit-Line 7T SRAM Cell for Near-Threshold Voltage Operation With Enhanced Performance and Energy in 14 nm FinFET Technology., , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 63-I (7): 1023-1032 (2016)A DLL With Dual Edge Triggered Phase Detector for Fast Lock and Low Jitter Clock Generator., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 59-I (9): 1860-1870 (2012)A 0.67nJ/S time-domain temperature sensor for low power on-chip thermal management., , , , and . ICCE, page 572-573. IEEE, (2013)Impact of fin thickness and height on read stability / write ability in tri-gate FinFET based SRAM., , , , and . ISOCC, page 479-482. IEEE, (2012)Coupling Delay Optimization by Temporal Decorrelation using Dual Threshold Voltage Technique., , , , and . DAC, page 732-737. ACM, (2001)