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Resonant-Clock Design for a Power-Efficient, High-Volume x86-64 Microprocessor., , , , , and . IEEE J. Solid State Circuits, 48 (1): 140-149 (2013)Design solutions for the Bulldozer 32nm SOI 2-core processor module in an 8-core CPU., , , , , , , , , and 4 other author(s). ISSCC, page 78-80. IEEE, (2011)Resonant clock design for a power-efficient high-volume x86-64 microprocessor., , , , , and . ISSCC, page 68-70. IEEE, (2012)ATPG for Timing Errors in Globally Asynchronous Locally Synchronous Systems., , , and . Journal of Circuits, Systems, and Computers, 12 (3): 305-332 (2003)A low-power distributed wide-band LNA in 0.18µm CMOS., , and . ISCAS (5), page 5055-5058. IEEE, (2005)40-Entry unified out-of-order scheduler and integer execution unit for the AMD Bulldozer x86-64 core., , and . ISSCC, page 80-82. IEEE, (2011)Configuring a load-balanced switch in hardware., , , and . Hot Interconnects, page 48-53. IEEE Computer Society, (2004)Using Hardware to Configure a Load-Balanced Switch., , , and . IEEE Micro, 25 (1): 70-78 (2005)Design of the Two-Core x86-64 AMD "Bulldozer" Module in 32 nm SOI CMOS., , , , , , , , and . IEEE J. Solid State Circuits, 47 (1): 164-176 (2012)Carrizo: A High Performance, Energy Efficient 28 nm APU., , , , , , , , , and 5 other author(s). IEEE J. Solid State Circuits, 51 (1): 105-116 (2016)