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AQUILA: An equivalence verifier for large sequential circuits.

, , and . ASP-DAC, page 455-460. IEEE, (1997)

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Logic synthesis and optimization algorithms. University of Illinois Urbana-Champaign, USA, (1991)An Efficient Sequential SAT Solver With Improved Search Strategies., , , , , and . DATE, page 1102-1107. IEEE Computer Society, (2005)Compact Vector Generation for Accurate Power Simulation., , , and . DAC, page 161-164. ACM Press, (1996)Logic Synthesis for Engineering Change., , , , and . DAC, page 647-652. ACM Press, (1995)DAG-Map: Graph-Based FPGA Technology Mapping for Delay Optimization., , , , and . IEEE Des. Test Comput., 9 (3): 7-20 (1992)Efficient Sum-to-One Subsets Algorithm for Logic Optimization., and . DAC, page 443-448. IEEE Computer Society Press, (1992)Incremental logic rectification., , and . VTS, page 143-149. IEEE Computer Society, (1997)SYLON-DREAM: a multi-level network synthesizer., and . ICCAD, page 552-555. IEEE Computer Society, (1989)An Improved Graph-Based FPGA Techology Mapping Algorithm For Delay Optimization., , , , and . ICCD, page 154-158. IEEE Computer Society, (1992)AutoFix: a hybrid tool for automatic logic rectification., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 18 (9): 1376-1384 (1999)