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Disambiguation of "Kajihara, Seiji"

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A diagnosis method for single logic design errors in gate-level combinational circuits.

, , , and . Syst. Comput. Jpn., 28 (6): 30-39 (1997)

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Seiji Miyashiro

Seiji Osawa

 

Other publications of authors with the same name

A novel capture-safety checking method for multi-clock designs and accuracy evaluation with delay capture circuits., , , , , , , and . VTS, page 197-202. IEEE Computer Society, (2012)Path delay test compaction with process variation tolerance., , , , , and . DAC, page 845-850. ACM, (2005)Special Section on Test and Verification of VLSIs., and . IEICE Trans. Inf. Syst., 91-D (3): 640-641 (2008)Acceleration Techniques of Multiple Fault Test Generation Using Vector Pair Analysis., , , and . IEICE Trans. Inf. Syst., 78-D (7): 811-816 (1995)A Statistical Quality Model for Delay Testing., , , , and . IEICE Trans. Electron., 89-C (3): 349-355 (2006)Don't Care Identification and Statistical Encoding for Test Data Compression., , , , and . IEICE Trans. Inf. Syst., 87-D (3): 544-550 (2004)On Design for IDDQ-Based Diagnosability of CMOS Circuits Using Multiple Power Supplies., , , , and . IEICE Trans. Inf. Syst., 88-D (4): 703-710 (2005)LCTI-SS: Low-Clock-Tree-Impact Scan Segmentation for Avoiding Shift Timing Failures in Scan Testing., , , , , and . IEEE Des. Test, 30 (4): 60-70 (2013)Partial scan design and test sequence generation based on reduced scan shift method., , and . J. Electron. Test., 7 (1-2): 115-124 (1995)Evaluation of Delay Testing Based on Path Selection., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 86-A (12): 3208-3210 (2003)