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Design Techniques for Embedded EEPROM Memories in Portable ASIC and ASSP Solutions.

, , , , , , and . MTDT, page 39-46. IEEE Computer Society, (2000)

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Evaluation of design for reliability techniques in embedded flash memories., , , and . DATE, page 1593-1598. EDA Consortium, San Jose, CA, USA, (2007)A statistical design method for Giga Bit memory arrays and beyond., , , , and . ICECS, page 970-973. IEEE, (2010)A comprehensive delay macro modeling for submicrometer CMOS logics., and . IEEE J. Solid State Circuits, 34 (1): 42-55 (1999)Design Techniques for Embedded EEPROM Memories in Portable ASIC and ASSP Solutions., , , , , , and . MTDT, page 39-46. IEEE Computer Society, (2000)Embedded EEPROM Speed Optimization Using System Power Supply Resources., , , , and . PATMOS, volume 3254 of Lecture Notes in Computer Science, page 381-391. Springer, (2004)A concurrent approach for testing address decoder faults in eFlash memories., , , , , and . ITC, page 1-10. IEEE Computer Society, (2007)Temperature Effect on Delay for Low Voltage Applications., , and . DATE, page 680-685. IEEE Computer Society, (1998)Test and Repair of Embedded Flash Memories.. ITC, page 1219. IEEE Computer Society, (2002)Delay modelling improvement for low voltage applications., , and . EURO-DAC, page 216-221. IEEE Computer Society, (1995)A 40ns Random Access Time Low Voltage 2Mbits EEPROM Memory for Embedded Applications., , , , , and . MTDT, page 81-85. IEEE Computer Society, (2003)