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Comparing Energy, Area, Delay Tradeoffs in Going Vertical with CMOS and Asymmetric HTFETs.

M. Kim, W. Cane-Wissing, J. Sampson, S. Datta, V. Narayanan, and S. Gupta. ISVLSI, page 303-308. IEEE Computer Society, (2015)

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Ashutosh Kumar Gupta

Ajay Kumar Gupta

Manoj Kumar Gupta

Rajender Kumar Gupta

Surender Kumar Gupta

Other publications of authors with the same name

ROBIN: Monolithic-3D SRAM for Enhanced Robustness with In-Memory Computation Support.S. Srinivasa, A. Ramanathan, X. Li, W. Chen, S. Gupta, M. Chang, S. Ghosh, J. Sampson, and V. Narayanan. IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (7): 2533-2545 (2019)High-performance low-energy STT MRAM based on balanced write scheme.D. Lee, S. Gupta, and K. Roy. ISLPED, page 9-14. ACM, (2012)Device/circuit interactions at 22nm technology node.K. Roy, J. Kulkarni, and S. Gupta. DAC, page 97-102. ACM, (2009)Read-enhanced spin memories augmented by phase transition materials (Invited).A. Aziz, and S. Gupta. MWSCAS, page 993-996. IEEE, (2017)Independently-Controlled-Gate FinFET 6T SRAM Cell Design for Leakage Current Reduction and Enhanced Read Access Speed.K. Ma, H. Liu, Y. Xiao, Y. Zheng, X. Li, S. Gupta, Y. Xie, and V. Narayanan. ISVLSI, page 296-301. IEEE Computer Society, (2014)Comparative Evaluation of Memory Technologies for Synaptic Crossbar Arrays- Part 2: Design Knobs and DNN Accuracy Trends.J. Victor, C. Wang, and S. Gupta. CoRR, (2024)An area efficient low-voltage 6-T SRAM cell using stacked silicon nanowires.Y. Huang, M. Chiang, S. Wang, and S. Gupta. ICICDT, page 117-120. IEEE, (2018)Valley-Coupled-Spintronic Non-Volatile Memories with Compute-In-Memory Support.S. Thirumala, Y. Hung, S. Jain, A. Raha, N. Thakuria, V. Raghunathan, A. Raghunathan, Z. Chen, and S. Gupta. CoRR, (2019)Exploiting ferroelectric FETs for low-power non-volatile logic-in-memory circuits.X. Yin, A. Aziz, J. Nahas, S. Datta, S. Gupta, M. Niemier, and X. Hu. ICCAD, page 121. ACM, (2016)FeFET-Based Synaptic Cross-Bar Arrays for Deep Neural Networks: Impact of Ferroelectric Thickness on Device-Circuit Non-Idealities and System Accuracy.C. Wang, J. Victor, A. Saha, X. Chen, M. Si, T. Sharma, K. Roy, P. Ye, and S. Gupta. DRC, page 1-2. IEEE, (2023)

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Disambiguation of "Gupta, Sumeet Kumar"

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Comparing Energy, Area, Delay Tradeoffs in Going Vertical with CMOS and Asymmetric HTFETs.

Please choose a person to relate this publication to

Ashutosh Kumar Gupta

Ajay Kumar Gupta

Manoj Kumar Gupta

Rajender Kumar Gupta

Surender Kumar Gupta

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Gupta, Sumeet Kumar"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Comparing Energy, Area, Delay Tradeoffs in Going Vertical with CMOS and Asymmetric HTFETs.

Please choose a person to relate this publication to

Ashutosh Kumar Gupta

Ajay Kumar Gupta

Manoj Kumar Gupta

Rajender Kumar Gupta

Surender Kumar Gupta

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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history of this post
URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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Comparing Energy, Area, Delay Tradeoffs in Going Vertical with CMOS and Asymmetric HTFETs.