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Towards modeling and integrated design automation of supercomputing clusters (MIDAS)., , , , , , , and . Comput. Sci. Res. Dev., 24 (1-2): 1-10 (2009)Custom Built Heterogeneous Multi-core Architectures (CUBEMACH): Breaking the conventions., , , , , and . IPDPS Workshops, page 1-15. IEEE, (2010)Performance and energy efficient cache system design: Simultaneous execution of multiple applications on heterogeneous cores., , , , , , , and . ISVLSI, page 200-205. IEEE Computer Socity, (2013)SCOC IP Cores for Custom Built Supercomputing Nodes., , , , , , , , , and 3 other author(s). ISVLSI, page 255-260. IEEE Computer Society, (2012)Compilation Accelerator on Silicon., , , , , , , , , and 3 other author(s). ISVLSI, page 267-272. IEEE Computer Society, (2012)Memory in processor: a novel design paradigm for supercomputing architectures., , , , and . SIGARCH Comput. Archit. News, 32 (3): 19-26 (2004)PASCOM: Power Model for Supercomputers., , and . ARCS, volume 3894 of Lecture Notes in Computer Science, page 326-340. Springer, (2006)A Non-Uniform Grid Based Ground Plane Model for High Performance Nodes: The Impact of Heterogeneous Cores on Ground Voltage Gradient., , , and . ISVLSI, page 49-54. IEEE Computer Society, (2009)DNA Based Evolutionary Approach for Microprocessor Design Automation., , and . ICANNGA (1), volume 4431 of Lecture Notes in Computer Science, page 11-22. Springer, (2007)Design for Testability of Functional Cores in High Performance Node Architectures., , and . DELTA, page 302-307. IEEE Computer Society, (2008)