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A Twin Memristor Synapse for Spike Timing Dependent Learning in Neuromorphic Systems.

, , , , , and . SoCC, page 37-42. IEEE, (2018)

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A Twin Memristor Synapse for Spike Timing Dependent Learning in Neuromorphic Systems., , , , , and . SoCC, page 37-42. IEEE, (2018)RTL-to-GDS Tool Flow and Design-for-Test Solutions for Monolithic 3D ICs., , , , , , , , , and 1 other author(s). DAC, page 101. ACM, (2019)Design, packaging, and architectural policy co-optimization for DC power integrity in 3D DRAM., , , , , , and . DAC, page 91:1-91:6. ACM, (2015)Pseudo-3D Approaches for Commercial-Grade RTL-to-GDS Tool Flow Targeting Monolithic 3D ICs., , , , and . ISPD, page 47-54. ACM, (2020)Compact-2D: A Physical Design Methodology to Build Commercial-Quality Face-to-Face-Bonded 3D ICs., , and . ISPD, page 90-97. ACM, (2018)Compact-2D: A Physical Design Methodology to Build Two-Tier Gate-Level 3-D ICs., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (6): 1151-1164 (2020)Unsupervised Digit Recognition Using Cosine Similarity In A Neuromemristive Competitive Learning System., , , , , , , and . ACM J. Emerg. Technol. Comput. Syst., 18 (2): 38:1-38:20 (2022)Built-in Self-Test and Fault Localization for Inter-Layer Vias in Monolithic 3D ICs., , , , , , , and . ACM J. Emerg. Technol. Comput. Syst., 18 (1): 22:1-22:37 (2022)Pseudo-3D Physical Design Flow for Monolithic 3D ICs: Comparisons and Enhancements., , , , and . ACM Trans. Design Autom. Electr. Syst., 26 (5): 37:1-37:25 (2021)Pin-in-the-middle: an efficient block pin assignment methodology for block-level monolithic 3D ICs., and . ISLPED, page 85-90. ACM, (2020)