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Disambiguation of "Chao, Kai-Yuan"

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Timing-Aware Layer Assignment for Advanced Process Technologies Considering via Pillars.

, , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (6): 1957-1970 (2022)

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Yuan-Hsin Chao

Kai-Yuan Wu

Hsi-Lin Chao

Kuo-Yih Chao

Zouheir Chaoui

 

Other publications of authors with the same name

Spare-cell-aware multilevel analytical placement., , , and . DAC, page 430-435. ACM, (2009)Is Your Layout-Density Verification Exact? - A Fast Exact Deep Submicrometer Density Calculation Algorithm., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 27 (4): 621-632 (2008)Optimal Double Via Insertion With On-Track Preference., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 29 (2): 318-323 (2010)Configurable multi-product floorplanning., , and . ASP-DAC, page 549-554. IEEE, (2010)Hybrid lithography optimization with E-Beam and immersion processes for 16nm 1D gridded design., , , and . ASP-DAC, page 707-712. IEEE, (2012)Coupling-aware Dummy Metal Insertion for Lithography., , , and . ASP-DAC, page 13-18. IEEE Computer Society, (2007)Lithography-aware layout modification considering performance impact., , , and . ISQED, page 437-441. IEEE, (2011)High-quality global routing for multiple dynamic supply voltage designs., , and . ICCAD, page 263-269. IEEE Computer Society, (2011)Post-routing redundant via insertion and line end extension with via density consideration., , and . ICCAD, page 633-640. ACM, (2006)Dummy fill density analysis with coupling constraints., , , , and . ISPD, page 3-10. ACM, (2007)