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Delay Estimates for Graphene Nanoribbons: A Novel Measure of Fidelity and Experiments with Global Routing Trees.

, , , , and . ACM Great Lakes Symposium on VLSI, page 263-268. ACM, (2016)

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Delay Estimates for Graphene Nanoribbons: A Novel Measure of Fidelity and Experiments with Global Routing Trees., , , , and . ACM Great Lakes Symposium on VLSI, page 263-268. ACM, (2016)Minimization of Switching Activity of Graphene Based Circuits., , , and . VLSID, page 139-144. IEEE, (2021)Max-Testable Class of Sequential Circuits having Combinational Test Generation Complexity., , , and . Asian Test Symposium, page 342-347. IEEE Computer Society, (2004)A new ALU architecture design using reversible logic., and . ISED, page 187-191. IEEE, (2016)A technique to construct global routing trees for graphene nanoribbon (GNR)., and . ISQED, page 111-118. IEEE, (2017)Co-Optimization of Test Wrapper Length and TSV for TSV Based 3D SOCs., , and . J. Electron. Test., 36 (2): 239-253 (2020)Genetic Algorithm Based Efficient Grouping Technique for Post Bond Test and Crosstalk Faults Among TSVs., , and . VLSID, page 730-735. IEEE, (2024)A Novel ALU Circuit based on Reversible Logic., and . J. Circuits Syst. Comput., 29 (11): 2050172:1-2050172:17 (2020)Boolean Difference Technique for Detecting All Missing Gate and Stuck-at Faults in Reversible Circuits., , , , and . Journal of Circuits, Systems, and Computers, 28 (12): 1950212:1-1950212:18 (2019)On Designing Testable Reversible Circuits Using Gate Duplication., , , , and . VDAT, volume 382 of Communications in Computer and Information Science, page 322-329. Springer, (2013)