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Restructuring field layouts for embedded memory systems.

, , , and . DATE, page 937-942. European Design and Automation Association, Leuven, Belgium, (2006)

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Restructuring field layouts for embedded memory systems., , , and . DATE, page 937-942. European Design and Automation Association, Leuven, Belgium, (2006)Composition-based Cache simulation for structure reorganization., , and . J. Syst. Archit., 56 (2-3): 136-149 (2010)Leakage power minimization for the synthesis of parallel multiplier circuits., and . ACM Great Lakes Symposium on VLSI, page 166-169. ACM, (2004)Tight integration of timing-driven synthesis and placement of parallel multiplier circuits., and . IEEE Trans. Very Large Scale Integr. Syst., 12 (7): 766-775 (2004)An integrated approach to timing-driven synthesis and placement of arithmetic circuits., and . ASP-DAC, page 155-158. IEEE Computer Society, (2004)