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Disambiguation of "Chatarasi, Prasanth"

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Vyasa: A High-Performance Vectorizing Compiler for Tensor Convolutions on the Xilinx AI Engine.

, , , , and . HPEC, page 1-10. IEEE, (2020)

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Other publications of authors with the same name

Evaluating Spatial Accelerator Architectures with Tiled Matrix-Matrix Multiplication., , , , , and . IEEE Trans. Parallel Distributed Syst., 33 (4): 1002-1014 (2022)Extending Polyhedral Model for Analysis and Transformation of OpenMP Programs., and . PACT, page 490-491. IEEE Computer Society, (2015)MARVEL: A Decoupled Model-driven Approach for Efficiently Mapping Convolutions on Spatial DNN Accelerators., , , , , , and . CoRR, (2020)Advancing Compiler Optimizations for General-Purpose & Domain-Specific Parallel Architectures.. Georgia Institute of Technology, Atlanta, GA, USA, (2021)base-search.net (ftgeorgiatech:oai:smartech.gatech.edu:1853/64099).Union: A Unified HW-SW Co-Design Ecosystem in MLIR for Evaluating Tensor Operations on Spatial Accelerators., , , , , , , and . PACT, page 30-44. IEEE, (2021)MAESTRO: A Data-Centric Approach to Understand Reuse, Performance, and Hardware Cost of DNN Mappings., , , , , and . IEEE Micro, 40 (3): 20-29 (2020)Experimental Insights from the Rogues Gallery., , , , , and . ICRC, page 80-87. IEEE, (2019)A Unified Approach to Variable Renaming for Enhanced Vectorization., , , and . LCPC, volume 11882 of Lecture Notes in Computer Science, page 1-20. Springer, (2018)Vyasa: A High-Performance Vectorizing Compiler for Tensor Convolutions on the Xilinx AI Engine., , , , and . HPEC, page 1-10. IEEE, (2020)Understanding Reuse, Performance, and Hardware Cost of DNN Dataflow: A Data-Centric Approach., , , , , and . MICRO, page 754-768. ACM, (2019)