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Disambiguation of "Karl, Eric"

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Timing error correction techniques for voltage-scalable on-chip memories.

, , and . ISCAS (4), page 3563-3566. IEEE, (2005)

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Karl Eric Thonner

Freerk Erichsen

Hauke Erichsen

Ull Erich

Gerda Erich

 

Other publications of authors with the same name

ElastIC: An Adaptive Self-Healing Architecture for Unpredictable Silicon., , and . IEEE Des. Test Comput., 23 (6): 484-490 (2006)Timing error correction techniques for voltage-scalable on-chip memories., , and . ISCAS (4), page 3563-3566. IEEE, (2005)A 4.6 GHz 162 Mb SRAM Design in 22 nm Tri-Gate CMOS Technology With Integrated Read and Write Assist Circuitry., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 48 (1): 150-158 (2013)Advances in Microprocessor Cache Architectures Over the Last 25 Years., , , , , , , , and . IEEE Micro, 41 (6): 78-88 (2021)A 10nm SRAM Design using Gate-Modulated Self-Collapse Write Assist Enabling 175mV VMIN Reduction with Negligible Power Overhead., , , , , , , and . VLSI Circuits, page 1-2. IEEE, (2020)A 23.6-Mb/mm $^2$ SRAM in 10-nm FinFET Technology With Pulsed-pMOS TVC and Stepped-WL for Low-Voltage Applications., , , , , and . IEEE J. Solid State Circuits, 54 (1): 210-216 (2019)A 0.6 V, 1.5 GHz 84 Mb SRAM in 14 nm FinFET CMOS Technology With Capacitive Charge-Sharing Write Assist Circuitry., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 51 (1): 222-229 (2016)5.6 Mb/mm2 1R1W 8T SRAM Arrays Operating Down to 560 mV Utilizing Small-Signal Sensing With Charge Shared Bitline and Asymmetric Sense Amplifier in 14 nm FinFET CMOS Technology., , , , , , and . IEEE J. Solid State Circuits, 52 (1): 229-239 (2017)Introduction to the Special Issue on the 2020 IEEE International Solid-State Circuits Conference (ISSCC)., , , , and . IEEE J. Solid State Circuits, 56 (1): 3-6 (2021)Ponte Vecchio: A Multi-Tile 3D Stacked Processor for Exascale Computing., , , , , , , , , and 8 other author(s). ISSCC, page 42-44. IEEE, (2022)