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A Loop-Based Apparatus for At-Speed Self-Testing., and . J. Comput. Sci. Technol., 16 (3): 278-285 (2001)The monotonic increasing relationship between average powers of CMOS VLSI circuits with and without delay and its applications., , , and . Sci. China Ser. F Inf. Sci., 45 (6): 401-415 (2002)Reliability-Oriented Placement and Routing Algorithm for SRAM-Based FPGAs., , and . IEEE Trans. Very Large Scale Integr. Syst., 22 (2): 256-269 (2014)HHC: Hierarchical hardware checkpointing to accelerate fault recovery for SRAM-based FPGAs., , , , , , and . IOLTS, page 193-198. IEEE, (2013)PUFPass: A password management mechanism based on software/hardware codesign., , , , , , and . Integr., (2019)New Methodologies for Parallel Architecture., , and . J. Comput. Sci. Technol., 26 (4): 578-587 (2011)BitXpro: Regularity-Aware Hardware Runtime Pruning for Deep Neural Networks., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 31 (1): 90-103 (2023)Data Remapping for Static NUCA in Degradable Chip Multiprocessors., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 23 (5): 879-892 (2015)DHSA: efficient doubly homomorphic secure aggregation for cross-silo federated learning., , , , , and . J. Supercomput., 79 (3): 2819-2849 (2023)Selected Transition Time Adjustment for Tolerating Crosstalk Effects on Network-on-Chip Interconnects., , , and . IEEE Trans. Very Large Scale Integr. Syst., 19 (10): 1787-1800 (2011)