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A 30.3dBm 1.9GHz-bandwidth 2×4-array stacked 5.3GHz CMOS power amplifier., , and . ISSCC, page 88-89. IEEE, (2013)A 0.7-V 870-µW Digital-Audio CMOS Sigma-Delta Modulator., , , , and . IEEE J. Solid State Circuits, 44 (4): 1078-1088 (2009)Substrate noise coupling through planar spiral inductor., , , , and . IEEE J. Solid State Circuits, 33 (6): 877-884 (1998)An IC for linearizing RF power amplifiers using envelope elimination and restoration., and . IEEE J. Solid State Circuits, 33 (12): 2252-2258 (1998)A CMOS oversampling bandpass cascaded D/A converter with digital FIR and current-mode semi-digital filtering., , , and . IEEE J. Solid State Circuits, 39 (4): 585-593 (2004)A calibration-free 800MHz fractional-N digital PLL with embedded TDC., , and . ISSCC, page 472-473. IEEE, (2010)A 65nm dual-band 3-stream 802.11n MIMO WLAN SoC., , , , , , , , , and 21 other author(s). ISSCC, page 170-172. IEEE, (2011)A Digitally Modulated Polar CMOS Power Amplifier With a 20-MHz Channel Bandwidth., , , , and . IEEE J. Solid State Circuits, 43 (10): 2251-2258 (2008)A 150-MS/s 8-b 71-mW CMOS time-interleaved ADC., , , and . IEEE J. Solid State Circuits, 40 (5): 1057-1067 (2005)Measuring and modeling the effects of substrate noise on the LNA for a CMOS GPS receiver., , , , and . IEEE J. Solid State Circuits, 36 (3): 473-485 (2001)