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VLSI design of dual-mode Viterbi/turbo decoder for 3GPP., , , и . ISCAS (2), стр. 773-776. IEEE, (2004)Low-Latency Quasi-Synchronous Transmission Technique for Multiple-Clock-Domain IP Modules., , , и . ISCAS, стр. 869-872. IEEE, (2007)Entropy-Assisted Multi-Modal Emotion Recognition Framework Based on Physiological Signals., , , , и . CoRR, (2018)Low-complexity Recurrent Neural Network-based Polar Decoder with Weight Quantization Mechanism., , , и . CoRR, (2018)A Reduced-Complexity Fast Algorithm for Software Implementation of the IFFT/FFT in DMT Systems., , и . EURASIP J. Adv. Signal Process., 2002 (9): 961-974 (2002)New Ping-Pong Scheduling for Low-Latency EMD Engine Design in Hilbert-Huang Transform., , и . IEEE Trans. Circuits Syst. II Express Briefs, 60-II (8): 532-536 (2013)Unsupervised Learning for Neural Network-based Polar Decoder via Syndrome Loss., и . CoRR, (2019)A memory-reduced log-MAP kernel for turbo decoder., , и . ISCAS (2), стр. 1032-1035. IEEE, (2005)On-Line MSR-CORDIC VLSI Architecture with Applications to Cost-Efficient Rotation-Based Adaptive Filtering Systems., , , и . SiPS, стр. 422-427. IEEE, (2006)An 8.29 mm2 52 mW Multi-Mode LDPC Decoder Design for Mobile WiMAX System in 0.13 µm CMOS Process., , , и . IEEE J. Solid State Circuits, 43 (3): 672-683 (2008)