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On Dynamic Speculative Thread Partitioning and the MEM-Slicing Algorithm.

, and . J. Univers. Comput. Sci., 6 (10): 908-927 (2000)

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Scaling Up the Atlas Chip-Multiprocessor., and . IEEE Trans. Computers, 54 (1): 82-87 (2005)An Instruction Throughput Model of Superscalar Processors., and . IEEE Trans. Computers, 57 (3): 389-403 (2008)The Offset Cube: An Optoelectronic Interconnection Network., , and . PCRCW, volume 853 of Lecture Notes in Computer Science, page 86-100. Springer, (1994)Real-time, parallel segmentation of high-resolution images on multi-core platforms., , and . J. Real Time Image Process., 13 (4): 685-702 (2017)HiPER-P: An Efficient, High-Performance Router for Multicomputer Interconnection Networks., , and . PCRCW, volume 1417 of Lecture Notes in Computer Science, page 103-118. Springer, (1997)Incorporating Multi-Chip Module Packaging Constraints into System Design., , , , , , and . ED&TC, page 508-513. IEEE Computer Society, (1996)Dynamic Strands: Collapsing Speculative Dependence Chains for Reducing Pipeline Communication., and . MICRO, page 7-17. IEEE Computer Society, (2004)Impact of Power Density Limitation in Gigascale Integration for the SIMD Pixel Processor., , and . ARVLSI, page 57-71. IEEE Computer Society, (1999)Estimating Potential Parallelism for Platform Retargeting., , , and . WCRE, page 55-64. IEEE Computer Society, (2002)Efficient Processing of Color Image Sequences Using a Color-Aware Instruction Set on Mobile Systems., and . ASAP, page 137-149. IEEE Computer Society, (2004)