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A 32nm fully integrated reconfigurable switched-capacitor DC-DC converter delivering 0.55W/mm2 at 81% efficiency., , , , , and . ISSCC, page 210-211. IEEE, (2010)A 65-nm CMOS I/Q RF Power DAC With 24- to 42-dB Third-Harmonic Cancellation and Up to 18-dB Mixed-Signal Filtering., , , , and . IEEE J. Solid State Circuits, 53 (4): 1127-1138 (2018)Integrated Regulation for Energy-Efficient Digital Circuits., and . IEEE J. Solid State Circuits, 43 (8): 1795-1807 (2008)Analysis and Design of Integrated Active Cancellation Transceiver for Frequency Division Duplex Systems., , , , , and . IEEE J. Solid State Circuits, 52 (8): 2038-2054 (2017)A Mixed-Signal RISC-V Signal Analysis SoC Generator With a 16-nm FinFET Instance., , , , , , , , , and 21 other author(s). IEEE J. Solid State Circuits, 54 (10): 2786-2801 (2019)Mechanical Computing Redux: Relays for Integrated Circuit Applications., , , , , and . Proc. IEEE, 98 (12): 2076-2094 (2010)Replica compensated linear regulators for supply-regulated phase-locked loops., , , , and . IEEE J. Solid State Circuits, 41 (2): 413-424 (2006)An Output Bandwidth Optimized 200-Gb/s PAM-4 100-Gb/s NRZ Transmitter With 5-Tap FFE in 28-nm CMOS., , , , , , , , and . IEEE J. Solid State Circuits, 57 (1): 21-31 (2022)A frequency-reconfigurable multi-standard 65nm CMOS digital transmitter with LTCC interposers., , , , , , , , and . A-SSCC, page 345-348. IEEE, (2014)A 4.78mm2 fully-integrated neuromodulation SoC combining 64 acquisition channels with digital compression and simultaneous dual stimulation., , , , , , , and . VLSIC, page 1-2. IEEE, (2014)