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A NUCA Substrate for Flexible CMP Cache Sharing., , , , , and . IEEE Trans. Parallel Distributed Syst., 18 (8): 1028-1040 (2007)A Neuroevolution Method for Dynamic Resource Allocation on a Chip Multiprocessor, , and . Proceedings of the INNS-IEEE International Joint Conference on Neural Networks, page 2355--2361. Piscataway, NJ, IEEE, (2001)On-Chip Interconnection Networks of the TRIPS Chip., , , , , , and . IEEE Micro, 27 (5): 41-50 (2007)Memory Systems., , and . The Computer Science and Engineering Handbook, CRC Press, (1997)Microscaling Data Formats for Deep Learning., , , , , , , , , and 23 other author(s). CoRR, (2023)TRIPS: A polymorphous architecture for exploiting ILP, TLP, and DLP., , , , , , , , , and . ACM Trans. Archit. Code Optim., 1 (1): 62-93 (2004)Changing Interaction of Compiler and Architecture., , , , , , , , , and 1 other author(s). Computer, 30 (12): 51-58 (1997)Multicore Model from Abstract Single Core Inputs., , , , and . IEEE Comput. Archit. Lett., 12 (2): 59-62 (2013)Dynamic vectorization in the E2 dynamic multicore architecture., , and . SIGARCH Comput. Archit. News, 38 (4): 27-32 (2010)Errata on "Measuring Experimental Error in Microprocessor Simulation"., , , , , , and . SIGARCH Comput. Archit. News, 30 (1): 2-4 (2002)