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Towards completely fair scheduling on asymmetric single-ISA multicore processors.

, , , , and . J. Parallel Distributed Comput., (2017)

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Using age registers for a simple load-store queue filtering., , , , and . J. Syst. Archit., 55 (2): 79-89 (2009)Reuse Detector: Improving the Management of STT-RAM SLLCs., , , , , , , , , and 1 other author(s). CoRR, (2024)Parallel Wavelet Transform for Large Scale Image Processing., , , and . IPDPS, IEEE Computer Society, (2002)Replacing Associative Load Queues: A Timing-Centric Approach., , , , , , , and . IEEE Trans. Computers, 58 (4): 496-511 (2009)Reducing Cache Hierarchy Energy Consumption by Predicting Forwarding and Disabling Associative Sets., , , , , and . J. Circuits Syst. Comput., (2012)Write-Aware Replacement Policies for PCM-Based Systems., , , , , and . Comput. J., 58 (9): 2000-2025 (2015)OpenIRS-UCM: an open-source multi-platform for interactive response systems., , , , , and . ITiCSE, page 232-237. ACM, (2012)An OS-Oriented Performance Monitoring Tool for Multicore Systems., , , , , , and . Euro-Par Workshops, volume 9523 of Lecture Notes in Computer Science, page 697-709. Springer, (2015)A Power-Efficient and Scalable Load-Store Queue Design., , , , , and . PATMOS, volume 3728 of Lecture Notes in Computer Science, page 1-9. Springer, (2005)Improving Pelifo Cache Replacement Policy: Hardware Reduction and Thread-Aware Extension., , , , , and . J. Circuits Syst. Comput., (2014)