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Disambiguation of "Dissanayake, Anjana"

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21.5 An Integrated 2.4GHz -91.5dBm-Sensitivity Within-Packet Duty-Cycled Wake-Up Receiver Achieving 2μ W at 100ms Latency.

, , , and . ISSCC, page 310-312. IEEE, (2021)

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Anjana Nityanandam

Anjana Singh

Anjana Devi

Anjana Buckow

 

Other publications of authors with the same name

23.2 A 1mm2 Software-Defined Dual-Mode Bluetooth Transceiver with 10dBm Maximum TX Power and -98.2dBm Sensitivity 2.96mW RX Power at 1Mb/s., , , , , , , , , and 7 other author(s). ISSCC, page 402-404. IEEE, (2024)A- 108dBm Sensitivity, -28dB SIR, 130nW to 41µW, Digitally Reconfigurable Bit-Level Duty-Cycled Wakeup and Data Receiver., , , , , , , , , and . CICC, page 1-4. IEEE, (2020)A 2.4 GHz-91.5 dBm Sensitivity Within-Packet Duty-Cycled Wake-Up Receiver., , , and . IEEE J. Solid State Circuits, 57 (3): 917-931 (2022)A 0.6V 785-nW Multimodal Sensor Interface IC for Ozone Pollutant Sensing and Correlated Cardiovascular Disease Monitoring., , , , and . IEEE J. Solid State Circuits, 56 (4): 1058-1070 (2021)A 2.5 ppm/°C 1.05-MHz Relaxation Oscillator With Dynamic Frequency-Error Compensation and Fast Start-Up Time., , , , , and . IEEE J. Solid State Circuits, 54 (7): 1952-1959 (2019)A 2.4GHz, -102dBm-sensitivity, 25kb/s, 0.466mW interference resistant BFSK multi-channel sliding-IF ULP receiver., , , and . ASP-DAC, page 319-320. IEEE, (2018)A 45-µW, 162.1-dBc/Hz FoM, 490-MHz Two-Stage Differential Ring VCO Without a Cross-Coupled Latch., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 65-II (11): 1579-1583 (2018)A 2.5 ppm/°C 1.05 MHz Relaxation Oscillator with Dynamic Frequency-Error Compensation and 8 µs Start-up Time., , , , , , , and . ESSCIRC, page 150-153. IEEE, (2018)A -106dBm 33nW Bit-Level Duty-Cycled Tuned RF Wake-up Receiver., , , , , , , , , and 2 other author(s). VLSI Circuits, page 86-. IEEE, (2019)A Multichannel, MEMS-Less -99dBm 260nW Bit-Level Duty Cycled Wakeup Receiver., , , , , and . VLSI Circuits, page 1-2. IEEE, (2020)