Author of the publication

A Neural Stimulator Frontend With High-Voltage Compliance and Programmable Pulse Shape for Epiretinal Implants.

, , , , , and . IEEE J. Solid State Circuits, 47 (1): 244-256 (2012)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

A Continuous-Time Hexagonal Field-Programmable Analog Array in 0.13μm CMOS with 186MHz GBW., , , , and . ISSCC, page 70-71. IEEE, (2008)Multirate cascaded continuous time Sigma-Delta modulators., , , and . ISCAS (4), page 225-228. IEEE, (2002)Design issues and performance limitations of a clock jitter insensitive multibit DAC architecture for high-performance low-power CT Sigma Delta modulators., , and . ISCAS (1), page 1076-1079. IEEE, (2004)A hexagonal Field Programmable Analog Array consisting of 55 digitally tunable OTAs., , , , and . ISCAS, page 2897-2900. IEEE, (2008)Fundamental limits of jitter insensitivity in discrete and continuous-time sigma delta modulators., , and . ISCAS (1), page 1037-1040. IEEE, (2003)A hybrid comparator for high resolution SAR ADC., , and . ISCAS, page 1050-1053. IEEE, (2016)Study of Compressed Sensing and Predictor Techniques for the Compression of Neural Signals under the Influence of Noise., and . EMBC, page 1102-1105. IEEE, (2018)A Nyquist Rate SAR ADC Employing Incremental Sigma Delta DAC Achieving Peak SFDR = 107 dB at 80 kS/s., , , and . IEEE J. Solid State Circuits, 53 (5): 1493-1507 (2018)Exploiting Weak PUFs From Data Converter Nonlinearity - E.g., A Multibit CT ΔΣ Modulator., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 63-I (7): 994-1004 (2016)A 0.4-V Gm-C Proportional-Integrator-Based Continuous-Time ΔΣ Modulator With 50-kHz BW and 74.4-dB SNDR., , , , , and . IEEE J. Solid State Circuits, 53 (11): 3256-3267 (2018)